The invention relates to a digital data buffer having a data path or a plurality of parallel data paths, each with a data input for receiving a digital data input signal, a clock input for receiving a clock input signal, and a data output providing a digital data output signal for application to a data destination device. The buffer is suitable for use with a data destination device that may be any device that requires a digital data input with an associated clock signal.
There is a need to have such a digital data buffer that is optimized in the setup/hold timing relationship and substantially free from phase jitter. There is a need for use of such a device in a memory system operating at clock frequencies as high as 800 MHz and above. Currently, a data buffer for this kind of application is not available.